1. Field of the Invention
The invention relates to an integrated circuit, and in particular, to a level shift circuit with the function of latching the state of an output node before the low voltage supply is off.
2. Description of the Related Art
For saving power, some of integrated circuits are operated at two different voltage levels or power domains. For instance, the circuits in the core of a integrated circuit often operates at a lower voltage (VDDL) of 3.3V than input/output circuits operating at a voltage (VDDH) of 5V in order to reduce power consumption and to enable the use of smaller transistors, thereby reducing the overall die size. Therefore, the integrated circuits frequently use level shifter circuits to adjust the voltage of the input signal so as to be correctly interpreted in the new power domain operating at a higher or lower voltage level.
FIG. 1 is a circuit diagram of a prior art level shifter circuit. Referring to FIG. 1, a level shifter circuit 100 includes an input unit 11, a level shifting unit 12 and an output unit 13. The voltage level (VDDL) of a first power supply provided for the input unit 11 is lower than the voltage level (VDDH) of a second power supply provided for the level shifting unit 12 and the output unit 13. After receiving a front-end input signal INP, the input unit 11 generates an input signal IN and a complementary input signal XIN. To save the power consumption, the first power source operating at a low voltage level is shut off. After the first power source is shut off, the voltages of the gates of both N-channel transistors 105 and 107 are dropped below the threshold voltage Vt such that the N-channel transistors 105 and 107 are shut off and the output node 112 and the complementary output node 111 are floated. In the worst case, the nodes 111 and 112 could float to the voltage of VDDH/2, thereby causing a static current drain through the inverters 108 and 109 in the output unit 13.
Because only one of both nodes 111 and 112 can be pulled to VDDH by using two P-channel transistors 104 and 106, the other node stays at the voltage of VDDH/2 for lack of a leaking path to the ground so that the P-channel and N-channel transistors of inverters 108 and 109 are simultaneously turned ON and there is a static current drain through the second power supply operating at a high voltage. Besides, the voltage of the output terminal 110 becomes indeterminable, which may result in errors of the following stages.
FIG. 2 is a circuit diagram of another prior art level shifter circuit. Referring to FIG. 2, a level shifter circuit 200 also includes an input unit 11, a level shifting unit 22 and an output unit 13. Additionally, in the level shifting unit 22, two P-channel transistors 204 and 206 are inserted to the original level shifting unit 12 in FIG. 1, allowing nodes 111 and 112 to pull down more quickly. As mentioned above, when the first power source operating at a low voltage is turned off, N-channel transistors 105 and 107 are dropped below the threshold voltage Vt such that the N-channel transistors 105 and 107 are shut off and P-channel transistors 204 and 206 are turned on. As regards other situations, nodes 111 and 112 may float just like FIG. 1. If the voltage of the nodes 111 and 112 is staying at VDDH/2, there is a static current drain through the second power supply operating at a high voltage and the voltage of the output terminal 110 becomes indeterminable.
FIG. 3 is a circuit diagram of still another prior art level shifter circuit. In U.S. Pat. No. 6,600,358, Chan discloses a level shifter circuit 300 as shown in FIG. 3, which includes a low voltage detector 320 for detecting the low voltage supply, and eliminates the current drain when the low voltage supply is off. When the low voltage supply is turned off, the input terminal 101 is isolated from the output terminal 110 to avoid the current drain caused by a floating of the gate. However, after the low voltage supply is turned off, the output terminal 110 of the level shifter circuit 300 is fixed at a certain voltage level, but not maintained at a state right before the low voltage supply was turned off. Besides, a lot of transistors are required in the low voltage detector 320. Meanwhile, the number of transistors in the low voltage detector 320 is increased as the voltage difference between two different power domains become larger, so that more stages are necessary for detecting the low voltage supply. Further, the circuit layout size of the level shifter circuit 300 is larger than those of conventional level shifter circuits.
FIG. 4 is a circuit diagram of another prior art level shifter circuit. In U.S. Pat. No. 6,819,159, Lencioni discloses a level shifter circuit 400 as shown in FIG. 4, which includes two level shifters 430 and 440 and two transistors 405 and 407. Two transistors 405 and 407 are used to improve the pull-down speed of the output terminal 110 in the level shifter circuit 400. When the first power supply is turned off, if the two level shifters 430 and 440 match with each other, two transistors 405 and 407 are used as a leaking path to the ground for both the complementary output node 111 and the output node 112, and there is no static current drain. However, owing to including two level shifters 430 and 440, the level shifter circuit 400 occupies a larger circuit size than conventional level shift circuits do. Also, the circuit layouts of the two level shifters 430 and 440 necessarily match each other, thereby increasing the complexity of circuit design.
Conventional level shifter circuits are numerous. However, the primary object of a level shifter circuit is to correctly adjust the voltage level of the input signal. Thereby, when the low voltage supply is turned off, it is important that there are no static current drain and a definite voltage level of the output terminal in a practical level shifter circuit, which should be small in layout size and easy in circuit design.